SM39R08A5 Datasheet, PDF (50/58 Pages) SyncMOS Technologies,Inc – Additional Baud Rate Generator

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel 3
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel 0
Mnemonic: ADCC2
Address: ACh
7
6
5
4
3
2
1
0
Reset
Start ADJUST -
-
-
ADCCH[2:0]
00H
Start: When this bit is set, the ADC will be start conversion continuous.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1: ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
Channel
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
ADJUST = 0:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] 00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
-
-
-
-
-
- ADCD[1] ADCD[0] 00H
ADJUST = 1:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
-
-
-
-
-
- ADCD[9] ADCD[8] 00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] 00H
ADCD[9:0]: ADC data register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver E SM39R08A5 06/30/2015
- 50 -