SM39R08A5 Datasheet, PDF (44/58 Pages) SyncMOS Technologies,Inc – Additional Baud Rate Generator

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
12.IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can be
selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can detects
START, repeated START and STOP signals in slave mode. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
IICCTL
IICS
IICA1
IICA2
IICRWD
IICEBT
Description Direct
IIC control
register
F9h
IIC status
register
F8h
IIC Address
1 register
FAh
IIC Address
2 register
FBh
IIC
Read/Write FCh
register
IIC Enaable
Bus
FDh
Transaction
Bit 7
IICEN
Bit 6 Bit 5 Bit 4
IIC function
MSS MAS AB_EN
Bit 3
BF_EN
-
MPIF LAIF RXIF TXIF
IICA1[7:1]
IICA2[7:1]
IICRWD[7:0]
FU_EN
-
Bit 2 Bit 1 Bit 0 RST
IICBR[2:0]
04H
RXAK
TXAK
RW,B
B
00H
MATCH1
or RW1
A0H
MATCH2
or RW2
60H
00H
00H
Mnemonic: IICCTL
7
6
5
4
3
IICEN MSS MAS AB_EN BF_EN
Address: F9h
2
1
0
Reset
IICBR[2:0]
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost
condition. Set this bit when multi-master and slave connection. Clear this bit when single master
to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit will
always generate a start condition to bus when MStart is set. Set this bit when multi-master and
slave connection. Clear this bit when single master to single slave.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver E SM39R08A5 06/30/2015
- 44 -