SM39R08A5 Datasheet, PDF (45/58 Pages) SyncMOS Technologies,Inc – Additional Baud Rate Generator

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
011
Fosc/256
100
Fosc/512
101
Fosc/1024
110
Fosc/2048
111
Fosc/4096
Mnemonic: IICS
7
6
-
MPIF
5
LAIF
4
RXIF
3
2
1
TXIF RXAK TxAK
Address: F8H
0
Reset
RW
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set.
Software need to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data
Buffer) is loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read
Write Data Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has
been received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will
set (NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW: Master Mode:
Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be
cleared. This bit can be cleared by software to return ready state.
Slave Mode:
The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,
the slave module received data on the IIC bus (SDA).(Slave mode only)
Fig. 11-1: Acknowledgement bit in the 9^th bit of a byte transmission
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver E SM39R08A5 06/30/2015
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