SM39R08A5 Datasheet, PDF (11/58 Pages) SyncMOS Technologies,Inc – Additional Baud Rate Generator

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
1.4. The Clock Output Selection
The SM39R08A5 can generate a clock output signal at P3.5. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0]
00
01
10
11
Mode.
GPIO (P3.5)
Fosc
Fosc/2
Fosc/4
1.5. RESET
1.5.1. Hardware RESET function
SM39R08A5 provides on-chip hardware RESET mechanism, the reset duration is programmable by writer or ICP.
on-chip hardware RESET duration
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2. Software RESET function
SM39R08A5 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic
Description
TAKEY Time Access Key register
SWRES Software Reset register
Direct Bit 7 Bit 6 Bit 5
Software Reset function
F7h
E7h
Bit 4 Bit 3
TAKEY [7:0]
SWRES [7:0]
Bit 2
Bit 1
Bit 0
RESET
00H
00H
1.5.3. Reset status
Mnemonic: RSTS
7
6
5
-
-
-
4
PDRF
3
2
WDTF SWRF
1
LVRF
Address: A1h
0
Reset
PORF 00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver E SM39R08A5 06/30/2015
- 11 -