SM39R08A5 Datasheet, PDF (25/58 Pages) SyncMOS Technologies,Inc – Additional Baud Rate Generator

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
6.2. Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
4
3
TF1 TR1 TF0 TR0
IE1
Address: 88h
2
1
0 Reset
IT1
IE0
IT0 00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
6.3. Enhance Interrupt Trigger SFR(ENHIT)
Mnemonic: ENHIT
7
6
5
4
3
2
- ENHIT1 -
ENHIT0
-
-
Address: E5h
1
0 Reset
-
-
07H
Note: It is supported the version E of MCU after.
ENHIT1: Interrupt 1 edge trigger control bit.
When ENHIT1 is set to 0 and IT1 is set to 1, The method of edge trigger is
falling edge trigger.
When ENHIT1 and IT1 both are set to 1, The method of edge trigger is rising
edge trigger.
ENHIT0=0
ENHIT0=1
IT0=0 INT0 low level trigger INT0 low level trigger
IT0=1 INT0 failing edge trigger INT0 rising edge trigger
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver E SM39R08A5 06/30/2015
- 25 -