RM0367 Datasheet, PDF (844/1009 Pages) STMicroelectronics – This reference manual targets application developers

RM0367
Low-power universal asynchronous receiver transmitter (LPUART)
30.7.7
Bit 2 NF: START bit Noise detection flag
This bit is set by hardware when noise is detected on the START bit of a received frame. It is
cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NF flag is set
during multibuffer communication if the EIE bit is set.
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register.
An interrupt is generated if EIE = 1 in the LPUART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the LPUART_ICR register.
An interrupt is generated if PEIE = 1 in the LPUART_CR1 register.
0: No parity error
1: Parity error
Interrupt flag clear register (LPUART_ICR)
Address offset: 0x20
Reset value: 0x0000
31
Res.
15
Res.
30
Res.
14
Res.
29
Res.
13
Res.
28
Res.
12
Res.
27
Res.
11
Res.
26
Res.
25
Res.
24
Res.
10
Res.
9
CTSCF
w
8
Res.
23
Res.
7
Res.
22
Res.
6
TCCF
w
21
Res.
5
Res.
20
19
WUCF Res.
w
4
3
IDLECF ORECF
w
w
18
Res.
2
NCF
w
17
CMCF
w
1
FECF
w
16
Res.
0
PECF
w
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 WUCF: Wakeup from Stop mode clear flag
Writing 1 to this bit clears the WUF flag in the LPUART_ISR register.
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
forced by hardware to ‘0’.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the LPUART_ISR register.
Bits 16:10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register.
Bits 8:7 Reserved, must be kept at reset value.
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