RM0367 Datasheet, PDF (341/1009 Pages) STMicroelectronics – This reference manual targets application developers

Analog-to-digital converter (ADC)
RM0367
Bit 22 VREFEN: V_REFINT enable
This bit is set and cleared by software to enable/disable the V_REFINT.
0: V_REFINT disabled
1: V_REFINT enabled
Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion
is ongoing).
Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for
all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0,
ADSTP=0, ADDIS=0 and ADEN=0).
Bits 17:0 Reserved, must be kept at reset value.
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