RM0367 Datasheet, PDF (178/1009 Pages) STMicroelectronics – This reference manual targets application developers

RM0367
Reset and clock control (RCC)
7.2.5
Note:
ENREF_HSI48 and EN_VREFINT in Section 10.2.3: Reference control and status register
(SYSCFG_CFGR3))
The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the
HSI48 RC is stable or not. At startup, the HSI48 RC output clock is not released until this bit
is set by hardware.
The HSI48 RC can be switched on and off using the HSI48ON bit in the Clock recovery RC
register (RCC_CRRCR).
PLL
The internal PLL can be clocked by the HSI16 RC or HSE clocks. It drives the system clock
and can be used to generate the 48 MHz clock for the USB peripheral (refer to Figure 17
and Section 7.3.1: Clock control register (RCC_CR).
The PLL input clock frequency must range between 2 and 24 MHz.
The desired frequency is obtained by using the multiplication factor and output division
embedded in the PLL:
• If the USB uses the PLL as clock source, the PLL VCO clock (defined by the PLL
multiplication factor) must be programmed to output a 96 MHz frequency (USBCLK =
PLLVCO/2).
• The system clock is derived from the PLL VCO divided by the output division factor.
The application software must set correctly the PLL multiplication factor to avoid exceeding
96 MHz as PLLVCO when the product is in range 1,
48 MHz as PLLVCO when the product is in range 2,
24 MHz when the product is in range 3.
It must also set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
The PLL configuration (selection of the source clock, multiplication factor and output division
factor) must be performed before enabling the PLL. Once the PLL is enabled, these
parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0.
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
An interrupt can be generated when the PLL is ready if enabled in the RCC_CIER register
(see Section 7.3.5).
For code example, refer to A.4.2: PLL configuration modification code example.
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