RM0367 Datasheet, PDF (602/1009 Pages) STMicroelectronics – This reference manual targets application developers

RM0367
Low-power timer (LPTIM)
24.4.10
Counter mode
The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be
used to count internal clock cycles. The CKSEL and COUNTMODE bits control which
source will be used for updating the counter.
In case the LPTIM is configured to count external events on Input1, the counter can be
updated following a rising edge, falling edge or both edges depending on the value written
to the CKPOL[1:0] bits.
The count modes below can be selected, depending on CKSEL and COUNTMODE values:
• CKSEL = 0: the LPTIM is clocked by an internal clock source
– COUNTMODE = 0
When the LPTIM is configured to be clocked by an internal clock source and the
LPTIM counter is configured to be updated by active edges detected on the LPTIM
external Input1, the internal clock provided to the LPTIM must be not be prescaled
(PRESC[2:0] = ‘000’).
– COUNTMODE = 1
The LPTIM external Input1 is sampled with the internal clock provided to the
LPTIM. Consequently, in order not to miss any event, the frequency of the
changes on the external Input1 signal should never exceed the frequency of the
internal clock provided to the LPTIM.
• CKSEL = 1: the LPTIM is clocked by an external clock source
COUNTMODE value is don’t care.
In this configuration, the LPTIM has no need for an internal clock source (except if the
glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as
system clock for the LPTIM. This configuration is suitable for operation modes where
no embedded oscillator is enabled.
For this configuration, the LPTIM counter can be updated either on rising edges or
falling edges of the input1 clock signal but not on both rising and falling edges.
Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM,
there is some initial latency (after the LPTIM is enabled) before the counter is
incremented. More precisely, the first five active edges on the LPTIM external Input1
(after LPTIM is enable) are lost.
For code example, refer to A.12.1: Pulse counter configuration code example.
24.4.11
Timer enable
The ENABLE bit located in the LPTIMx_CR register is used to enable/disable the LPTIM.
After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is
actually enabled.
The LPTIMx_CFGR and LPTIMx_IER registers must be modified only when the LPTIM is
disabled.
24.4.12
Encoder mode
This mode allows handling signals from quadrature encoders used to detect angular
position of rotary elements. Encoder interface mode acts simply as an external clock with
direction selection. This means that the counter just counts continuously between 0 and the
auto-reload value programmed into the LPTIMx_ARR register (0 up to ARR or ARR down to
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