RM0367 Datasheet, PDF (843/1009 Pages) STMicroelectronics – This reference manual targets application developers

Low-power universal asynchronous receiver transmitter (LPUART)
RM0367
Bit 7 TXE: Transmit data register empty
This bit is set by hardware when the content of the LPUART_TDR register has been
transferred into the shift register. It is cleared by a write to the LPUART_TDR register.
An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register.
0: data is not transferred to the shift register
1: data is transferred to the shift register)
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. It is cleared by
software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the
LPUART_TDR register.
An interrupt is generated if TCIE=1 in the LPUART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The
RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register.
An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register.
0: data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the LPUART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0),
whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. It is cleared by a software,
writing 1 to the ORECF, in the LPUART_ICR register.
An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multibuffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in
the LPUART_CR3 register.
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