RM0367 Datasheet, PDF (497/1009 Pages) STMicroelectronics – This reference manual targets application developers

General-purpose timers (TIM2/TIM3)
RM0367
21.3.15
Note:
Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 139: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.
The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.
Using one timer as prescaler for another timer
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Figure 139. Master/Slave timer example
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For example, you can configure Timer x to act as a prescaler for Timer y. Refer to
Figure 139. To do this:
1. Configure Timer x in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIMx_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIMy_SMCR register (writing TS=000).
3. Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the
periodic Timer x trigger signal (which correspond to the timer x counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
For code example, refer to A.11.17: Timer prescaling another timer code example.
If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer y.
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