TDA7590_09 Datasheet, PDF (8/42 Pages) STMicroelectronics – Digital signal processing IC for speech and audio applications

Pin description
TDA7590
2.2
Pin function
Table 2.
N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin function
Name
Type
Description
SRD1/TI02
STD1
SC02
SC01
DE_N
NMI_N
I/O Serial receive data. Serial input data for receiver. Timer 2 input/output.
I/O Serial transmit data. Serial output data from transmitter.
I/O
Serial control 2.Transmitter frame sync only in asynchronous mode,
transmitter and receiver frame sync in synchronous mode.
Serial control 1. Receive frame sync in asynchronous mode, output
I/O
from transmitter 2 or serial flag 1 in synchronous mode.
I/O Test data output (input/output). Debug request input and acknowledge output.
Non-maskable interrupt/ PINIT. Used to enable the PLL during RESET
I
and as a non-maskable interrupt at all other times.
SRD0
IOVDD
IOVSS
STD0
I/O Serial receive data. Serial input data for receiver.
I IO power supply.
I IO ground.
I/O Serial Transmit Data. Serial output data from transmitter.
SC10/SCL
ESSI1 serial control 0. Receive clock in asynchronous mode, output from
I/O transmitter or serial flag in synchronous mode.
I²C SCL serial clock line.
SC00
RXD
I/O
Serial control 0. Receive clock in asynchronous mode, output from transmitter
1 or serial flag 0 in synchronous mode.
I/O SCI receive data. Receives byte-oriented serial data.
TXD
SCLK
SCK1/TI01
SCK0
RESETN
SCANEN
TESTEN
COREVSS
COREVDD
I/O SCI read enable. Transmits serial data from SCI transmit shift register.
SCI serial clock. Input or output clock from which data is transferred in
I/O synchronous mode and from which the transmit and/or receive baud rate is
derived in asynchronous mode.
Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
I/O ^{bit clock for both receiver and transmitter in synchronous mode.}
Timer 1 input/output.
I/O
Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
bit clock for both receiver and transmitter in synchronous mode.
I System reset. A low level applied to RESET_N input initializes the IC.
I
SCAN enable. When active with TESTEN also active, controls the shifting of
the internal scan chains.
Test enable. When active, puts the chip into test mode and muxes the XTI
I clock to all flip-flops. When SCANEN is also active, the scan chain shifting is
enabled.
I Core ground.
I Core power supply.
TIO0
VSSSUB
I/O Timer 0 input/output.
I Analog substrate isolation.
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