TDA7590_09 Datasheet, PDF (25/42 Pages) STMicroelectronics – Digital signal processing IC for speech and audio applications

TDA7590
LOCK
OUTLOCK
MF0
MF1
MF2
MF3
MF4
MF5
MF6
PLLIE
PWRDN
DITEN
FRACEN
PEN
EQU
6
EQU
7
EQU
8
EQU
9
EQU
10
EQU
11
EQU
12
EQU
13
EQU
14
EQU
15
EQU
16
EQU
17
EQU
18
EQU
19
; PLL Lock Indication bit
; PLL Lost Lock bit
; Multiplication bit 0
; Multiplication bit 1
; Multiplication bit 2
; Multiplication bit 3
; Multiplication bit 4
; Multiplication bit 5
; Multiplication bit 6
; PLL interrupt enable
; PLL power down
; Dither Enable
; PLL Fractional-N function enable
; PLL Enable
;;; Bit Definitions for PLL_CLKCNTL
DSPDF0
EQU
0
; DSP clock divider factor 0
DSPDF1
EQU
1
; DSP clock divider factor 1
DSPDF2
EQU
2
; DSP clock divider factor 2
DSPDF3
EQU
3
; DSP clock divider factor 3
; Reserved
DCKSRC
EQU
6
; DSP clock source 0->XTI/(DSPDF3:0 + 1)
;
1->VCO/(DSPDF3:0 + 1)
DACLKEN
EQU
7
; Enable bit for oversampling clock
MFSDF0
EQU
8
; Oversampling multiple bit 0
MFSDF1
EQU
9
; Oversampling multiple bit 1
MFSDF2
EQU
10
; Oversampling multiple bit 2
MFSDF3
EQU
11
; Oversampling multiple bit 3
MFSDF4
EQU
12
; Oversampling multiple bit 4
MFSDF5
EQU
13
; Oversampling multiple bit 5
MFSDF6
EQU
14
; Oversampling multiple bit 6
SEL0
EQU
15
; Sampling multiple select bit 0
SEL1
EQU
16
; Sampling multiple select bit 1
SEL2
EQU
17
; Sampling multiple select bit 2
DSP_XTI
EQU
18
; DSP_XTI =0 -> Use VCO/DSPDF
for DCLK
; DSP_XTI =1 -> Use XTI
for DCLK
DAC_SEL
EQU
19
; Selects between VCO and ext_dac_clk
XTLD
EQU
20
; Disables the external crystal when set
;------------------------------------------------------------------------
;
EQUATES for I/O Port Programming
;------------------------------------------------------------------------
;
Register Addresses
HDR
EQU
$FFFFC9
; PS- Host port GPIO data Register
HDDR
EQU
$FFFFC8
; PS- Host port GPIO direction Register
PCRC
EQU
$FFFFBF
; Port C Control Register
PRRC
EQU
$FFFFBE
; Port C Direction Register
PDRC
EQU
$FFFFBD
; Port C GPIO Data Register
PCRD
EQU
$FFFFAF
; Port D Control register
PRRD
EQU
$FFFFAE
; Port D Direction Data Register
PDRD
EQU
$FFFFAD
; Port D GPIO Data Register
PCRE
EQU
$FFFF9F
; Port E Control register
PRRE
EQU
$FFFF9E
; Port E Direction Register
PDRE
EQU
$FFFF9D
; Port E Data Register
OGDB
EQU
$FFFFFC
; OnCE GDB Register
Appendix 1
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