TDA7590_09 Datasheet, PDF (21/42 Pages) STMicroelectronics – Digital signal processing IC for speech and audio applications

TDA7590
DSP peripherals
7.7
Timers and watchdog block
The timers and watchdog block consists of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its own
register set.
Each timer has the following capabilities:
● Uses internal or external clocking.
● Interrupts the Mozart after a specified number of events (clocks).
● Signals an external device after counting internal events.
● Triggers DMA transfers after a specified number of events (clocks) occurs.
● Connects to the external world through designated pins TIO[0-2] for timers 0-2.
When TIO is configured as an
● Input: timer functions as an external event counter. Timer measures external pulse
width/signal period.
● Output: timer functions as a:
– Timer
– Watchdog timer
– Pulse-width modulator.
7.8
PLL
The PLL generates the following clocks:
● DCLK: DSP core clock
● DACLK: ADC and DAC clock
● LRCLK: left/right clock for the SAI and the CODEC
● SCLK: shift serial clock for the SAI and the CODEC
7.9
CODEC cell
The main features of the CODEC cell are listed below:
● 20 bits stereo DAC, and 18 bits ADC
● I²S format
● Oversampling ratio: 512
● Sampling rates of 8 kHz to 48 kHz
The analog interface is in the form of differential signals for each channel. The interface on
the digital side has the form of an SAI interface and can interface directly to an SAI channel
and then to the DSP core.
DCLK can be supplied either by the internal PLL or by external, to allow synchronization
with external anal digital sources.
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