STE2001 Datasheet, PDF (8/36 Pages) STMicroelectronics – 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2001
Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)
0123
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
124 125 126 127
D00IN1138
Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
0123
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
124 125 126 127
D00IN1139
Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)
127 126 125 124
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
3210
D00IN1140
Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)
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127 126 125 124
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
3210
D00IN1141