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STE2001 Datasheet, PDF (6/36 Pages) STMicroelectronics – 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
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STE2001
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
TfDA Cb=100pF
TfDA Cb=400pF
Cb Capacitive load for SDAH and
SCLH
Cb Capacitive load for SDAH + SDA
line and SCLH + SCL line
TSW
note 5
PARALLEL INTERFACE
TCY(EN) Enable Cycle Time
VDD = 4.5V; Write
TW(EN) Enable Pulse width
VDD = 4.5V; Write
TSU(A) Address Set-up Time
VDD = 4.5V; Write
TH(A) Address Hold Time
VDD = 4.5V; Write
TSU(D) Data Set-Up Time
VDD = 4.5V; Write
TH(D) Data Hold Time
VDD = 4.5V; Write
SERIAL INTERFACE
FSCLK Clock Frequency
VDD = 4.5V
VDD1 = 1.8V
TCYC Clock Cycle SCLK
VDD = 4.5V
TPWH1 SCLK pulse width HIGH
VDD = 4.5V
TPWL1 SCLK Pulse width LOW
VDD = 4.5V
TS2 SCE setup time
TH2 SCE hold time
TPWH2 SCE minimum high time
TH5 SCE start hold time
Note 8
TS3 SD/C setup time
TH3 SD/C hold time
TS4 SDIN setup time
TH4 SDIN hold time
Min.
100
Typ.
25
120
Max.
400
Unit
ns
ns
pF
400
pF
10
ns
125
ns
60
ns
30
ns
50
ns
30
ns
50
ns
8
MHz
5
MHz
125
ns
70
ns
70
ns
50
ns
50
ns
60
ns
60
ns
60
ns
40
ns
40
ns
40
ns
Notes: 1. Fframe = f5--o--2-s--0-c-
2. RES may be LOW or HIGH before VDD1 goes HIGH.
3. If Tw(RES) is longer than 500ns (typical) a reset may be generated.
4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with
an input voltage swing of VSS to VDD
5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.
6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with TSW
7. Cb is the capacitive load for each bus line.
8. TH5 is the time from the previous SCLK positive edge to the negative edge of SCE
9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
10.CVLCD is the filterin g capacitor on VLCDOUT
11.If Tw(RES) is shorter than max. value a reset pulse is rejected.
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