STE2001 Datasheet, PDF (10/36 Pages) STMicroelectronics – 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2001
MUX 33 Mode
When using the 1:33 MUX ratio (MUX bit Set), the memory map is changed so that the only ”active” row drivers
are the ones related to Bank4 to Bank7.
When writing data RAM, as for Mux 65, four addressing mode are provided. The memory matrix is written as in
mux 65 mode so the user must take care of updating X and Y pointers to fill the memory matrix in the correct
way.
In MUX 33 mode only the MUX 33 memory logic matrix is read. The MY bit control the reading process. If MY
is set to a logic zero the row reading sequence is 0-1-2..........33 (fig.11). If MY is set to a logic one the reading
sequence is 32....1-33 (Fig 12).
The icon row (BANK8) is always the last being output either MY bit is a logic one or zero.
The functions related to bit TRS is the same as in MUX 65 mode.
In fig. 11 is shown the output drivers pad connection for MUX 33 mode. Note that the unused BANK 0-3 row
drivers become columns drivers.
If a 33x128 LCD matrix is driven, the output row drivers R0-R15 and R32-R47 must be floating.
Figure 10. Physical 65x128 memory matrix and 33x128 correspondence
01
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
14 15 16 17 18
109 110 111 112 113 126 127
NOT USED
D00IN1146
R16-R23
R24-R31
R48-R55
R56-R63
R64
D00IN1147
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