STE2001 Datasheet, PDF (19/36 Pages) STMicroelectronics – 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

Figure 19. communication protocol
STE2001
WRITE MODE
STE2001 ACK
STE2001 ACK
STE2001 ACK
STE2001 ACK
STE2001 ACK
S
S 0 1 1 1 1 0 A 0 A 1 DC Control Byte A DATA Byte A 0 DC Control Byte A DATA Byte A P
0
R/W Co
SLAVE ADDRESS
READ MODE
STE2001 ACK
COMMAND WORD
MASTER
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
S
S011110A1A
0
P
SR
011110A /
CD0 _{0 0 0 0 0A}
0W
oC
R/W
D01IN1247
STE2001
SLAVE ADDRESS
CONTROL BYTE
SERIAL INTERFACE
The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor.
It consists of four lines: one for data signals (SDIN), one for clock signals (SCLK), one for the peripheral enable
(SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral
power consumption is zero.
The STE2001 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-
ter. The STE2001 is only able to receive data.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
While SCE pin is high the serial interface is kept in reset.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the
eighth SCLK clock pulse during every byte transfer.
If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
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