STE2001 Datasheet, PDF (1/36 Pages) STMicroelectronics – 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2001
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
PRODUCT PREVIEW
s 65 x 128 bits Display Data RAM
s Configurable matrix: 65 x 128 or 33 x 128
s Programmable (65/33) MUX rate
s Row by Row Scrolling
s Automatic data RAM Blanking procedure
s Selectable Input Interface:
• I²C Bus Fast and Hs-mode (read and write)
• Parallel Interface (write only)
• Serial Interface (write only)
s Fully Integrated Oscillator requires no external
components
s Fully Integrated Configurable LCD bias voltages
generator with:
• Selectable (5X, 4X, 3X, 2X) multiplication factor
• Effective sensing for High Precision Output
• Four selectable temperature compensation
coefficients
s Designed for chip-on-glass (COG) applications
s Programmable bottom row pads mirroring and
top row pads mirroring for compatible with both
TCP and COG applications
s Low Power Consumption, suitable for battery
operated systems
s Logic Supply Voltage range from 1.9 to 5V
s High Voltage Generator Supply Voltage range
from 2.4 to 4.5V
s Display Supply Voltage range from 4.5 to 9V
DESCRIPTION
The STE2001 is a low power CMOS LCD controller
driver. Designed to drive a 65 rows by 128 columns
graphic display, provides all necessary functions in a
single chip, including on-chip LCD supply and bias
voltages generators, resulting in a minimum of exter-
nals components and in a very low power consump-
tion. The STE2001 features three standard interfaces
(Serial, parallel, I²C) for ease of interfacing with the
host µcontroller.
Type
Ordering Number
Bumped Wafers
STE2001DIE1
Bumped Dice on Waffle Pack
STE2001DIE2
Figure 1. Block Diagram
CO to C127
R0 to R64
OSC
VLCDIN
VLCDSENSE
VLCDOUT
RES
VDD1,2,3
V_SS1,2
SEL1,2
OSC
TIMING
GENERATOR
COLUMN
DRIVERS
BIAS VOLTAGE
GENERATOR
CLOCK
DATA
LATCHES
HIGH VOLTAGE
GENERATOR
RESET
65 x 128
RAM
ROW
DRIVERS
SHIFT
REGISTER
SCROLL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
DISPLAY
CONTROL
LOGIC
TEST
TEST_0_13
BSY_FLG
I2CBUS
PARALLEL
SERIAL
SAO SCL SDA_IN SDA_OUT DB0 to DB7 E PD/C SCE SDIN SCLK SD/C ^D00IN1137
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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