M39432 Datasheet, PDF (8/28 Pages) STMicroelectronics – Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM

M39432
Table 4. This consists of the writing of three
specific data bytes at three specific memory
locations (each location on a different page) as a
prefix to reading the OTP row content.
When accessing the OTP row, only the least
significant bits of the address bus (A0 to A6) are
decoded (of which A6 must be low).
Each Read of the OTP row has to be followed by
the Return instruction (as shown in Table 4).
Read the Flash Sector Protection Status
There are two alternative methods for reading the
Flash Sector Protection Status: using a Verify
operation with A9=V_ID (as described on page 18)
or using a Read instruction as described in the
section entitled “Read the Manufacturer Identifier”,
starting on page 7.
Using the Read instruction, the logic levels on A0,
A1, A6 select the correct instruction, while A16,
A17 and A18 specify which sector is being
addressed. This returns the value 01h if the Flash
sector is protected, and the value 00h if the Flash
sector is not protected.
Read the Status Bits
The latency period of Write, Erase and Program
cycles can be monitored by the application
software, by using the M39432 status bits. The
Ready/Busy pin provides the status information
during a write cycle to the EEPROM block (though
not to the Flash memory block). An internal status
register carries the status information during a
programming or erase cycle. A Read operation,
during the program or write cycle, causes the
contents of this register to be presented to the I/O
ports (DQ0-DQ7), as summarized in Table 6.
Data Polling flag, DQ7. The I/O lines (DQ0-
DQ7) are first used as inputs, carrying the data
that is to be written to the EEPROM or
programmed in the Flash memory. Once the Write
or Program cycle is underway, these lines become
outputs (and can be read using a normal Read
operation). The value presented on DQ7 is the
inverse of the data bit that was presented by the
user. When the cycle is complete, the lines remain
as outputs, and the value that is presented on DQ7
is the non-inverted value that was originally
specified for writing.
The suitable algorithm for using this method of
polling is shown in Figure 4. When a Write or
Program cycle is in progress, data bit DQ7 is set to
the complement of the original data bit 7 (or to ‘0’
in the case of an Erase cycle in the Flash memory
block). When DQ7 is identical to the old data (or to
‘1’ in the case of an Erase cycle in the Flash
memory block) and the Error bit (DQ5) is still ’0’,
the cycle is complete.
For the flash memory block, data Polling is
effective after the fourth pulse on the W line for
Figure 5. Data Toggle Flowchart
START
READ
DQ5 & DQ6
DQ= 6
NO
TOGGLE
YES
NO _DQ5
=1
YES
READ DQ6
DQ= 6
NO
TOGGLE
YES
FAIL
PASS
AI01370
Program cycles, and after the sixth pulse on the W
line for Erase cycles. The Data Polling Read
instruction must address the same location as the
byte that is being programmed, or within the same
Flash sector as the one that is being erased.
Toggle flag, DQ6. During an internal Write,
Program or Erase cycle, DQ6 toggles between ’0’
and ’1’, on successive Read accesses to any byte
of the memory (when either G, EE or EF is held
low).
When the internal cycle is complete, the toggling is
stopped, and the data read on DQ0-DQ7 is that of
the addressed memory byte. A subsequent
Reading at the same address will result in the
same data being read.
This alternative method for detecting when the
internal Write, Program or Erase cycle has
completed, is shown in the flowchart in Figure 5.
When an internal cycle is in progress, data bit DQ6
toggles between ‘1’ and ‘0’ for successive Read
operations. When DQ6 no longer toggles and the
Error bit DQ5 is ’0’, the operation is complete. To
determine if DQ6 has toggled, each poll requires
two consecutive Read operations to see if the data
read is the same each time.
For the flash memory block, data Toggling is
effective after the fourth pulse on the W line for
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