M39432 Datasheet, PDF (3/28 Pages) STMicroelectronics – Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM

Figure 3. Flash Block Sectors
A18 A17 A16
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
AI01362B
M39432
64K Bytes Block
64K Bytes Block
64K Bytes Block
64K Bytes Block
64K Bytes Block
TOP
BOTTOM
ADDRESS ADDRESS
7FFFFh 70000h
6FFFFh 60000h
5FFFFh 50000h
4FFFFh 40000h
3FFFFh 30000h
2FFFFh 20000h
1FFFFh 10000h
0FFFFh 00000h
Data Input/Output (DQ0-DQ7)
During a Write operation, one data byte is latched
into the device when Write Enable (W) and one
Chip Enable (EF or EE) are driven low.
During a Read operation, the output presented on
these pins is valid when Output Enable (G) and
one Chip Enable (EF or EE) are driven low. The
output is high impedance when the chip is
deselected (both EE and EF driven high) or the
outputs are disabled (G driven high).
Read operations are used to output:
– bytes in the Flash memory block
– bytes in the EEPROM block
– the Manufacturer Identifier
– the Flash Sector Protection Status
– the Flash Block Identifier
– the EEPROM Identifier
– the OTP row.
Chip Enable (EE and EF)
Each Chip Enable (EE or EF) causes the memory
control logic, input buffers, decoders and sense
amplifiers to be activated. When the EE input is
driven high, the EEPROM memory block is not
selected; when the EF input is driven high, the
Flash memory block is not selected. Attempts to
access both EEPROM and Flash blocks (EE low
and EF low) are forbidden. Switching between the
two chip enables (EE and EF) must not be made
on the same clock cycle, a delay of greater than
t_EHFL must occur.
The M39432 is in stand-by mode when both EF
and EE are high (when no internal Erase or
programming cycle is running). The power
consumption is reduced to the stand-by level and
the outputs are held in the high state, independent
of the Output Enable (G) or Write Enable (W)
inputs.
After 150 ns of inactivity, and when the addresses
are driven at CMOS levels, the chip automatically
enters a pseudo-stand-by mode. Power
consumption is reduced to the CMOS stand-by
level, while the outputs continue to drive the bus.
Output Enable (G)
The Output Enable gates the outputs through the
data buffers during a Read operation. The data
outputs are left floating in their high impedance
state when the Output Enable (G) is high.
During Sector Protect (Figure 8) and Sector
Unprotect (Figure 9) operations (for the Flash
memory block only), the G input must be held at
V_ID (as specified in Table 11).
Write Enable (W)
Addresses are latched on the falling edge of W,
and Data Inputs are latched on the rising edge of
W.
Ready/Busy (R/B)
When the EEPROM block is engaged in an
internal Write cycle, the Ready/Busy output shows
the status of the device:
– R/B is 0 when a Write cycle is in progress
– R/B is Hi-Z when no Write cycle is in progress
The Ready/Busy pin does not show the status of a
Program or Erase cycle in the Flash memory.
This pin can be used to show the status of the
EEPROM block, even when reading data (or
fetching instructions) from the Flash memory
block.
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