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AN910 Datasheet, PDF (37/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING
ST7 AND ST9 PERFORMANCE BENCHMARKING
7.3.10 80C51 MCU core
Programming model
Register file &
Accumulator
- general registers
4 banks of eight 8-bit registers
they are mapped in data memory
- special function registers
one 8-bit accumulator
16-bit program counter
16-bit data pointer register
useable as two 8-bit registers
8-bit stack pointer
condition code register
peripheral registers
they are mapped in data memory
- multitasking capabilities
context switching with banked registers
MOV A,(R1)
ADD A,#A0
Instruction set
Cisc encoding
- CPI
12 cycles to 48 cycles
- average CPI
between 18 and 20 cycles
- IL
1 byte to 3 bytes
- average IL
between 1 and 2 bytes
- special addressing modes
16-bit addressing with data pointer register
register/stack pointer/data pointer register indirect
stack pointer relative
- special instructions
exchange accumulator and register/direct byte
compare/decrement & branch like
bit test & bit clear & jump
memory-to-memory moves
direct to direct
direct to indirect
80C51 CPU
Core internal buses
16-bit address bus, 8-bit data bus
(to be confirmed)
Instruction processing
Standard
- sequential processing
Arithmetic Logic Unit
+/x
8-bit datapath
- 8-bit operations
- special functions
8x8 unsigned multiplication
16/8 unsigned division
48 cycles
48 cycles
On-chip/Off-chip buses
- on-chip buses
8/16-bit address bus
8-bit data memory bus
8-bit program memory bus
- off-chip buses
8/16-bit address bus
8-bit data/program memory bus
the two buses are multiplexed
the two buses are multiplexed with ports
Memory Spaces
Harvard organization
- linear data/program memory space
data memory space
64 kbytes
first 128-byte zero page
lowest 32-byte banked register space
16-byte bit addressable space
special function register space (logically separate)
128-byte special function register space
direct addressable only
program memory space
64 kbytes
first 128-byte zero page
first 24-byte interrupt vector table = 5 interrupts
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