AN910 Datasheet, PDF (3/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING

ST7 AND ST9 PERFORMANCE BENCHMARKING
2 OVERVIEW OF THE MCU CORES
The set of MCUs evaluated is composed of various 8-bit, 8/16-bit, and 16-bit
microcontrollers with accumulator, register file or mixed architectures.
Table 2 is an overview of the MCU cores.
Table 2. MCU cores overview
MCU name
Architecture
Short core description
Freq¹⁾
80C51XA
PHILIPS
16-bit;
register file
eXtended Architecture (XA) of 80C51’s - upward compatible
8/16-bit register bus - 16-bit data/program memory buses
20 MHz
register file programming model with sixteen 16-bit banked registers
68HC16
MOTOROLA
16-bit;
two
accumulators
core architecture superset of 68HC11’s - upward compatible
accumulator programming model with two 16-bit accumulators, and 16 MHz
three 16-bit index registers (all with 4-bit extensions)
68HC12
MOTOROLA
16-bit;
two
accumulators
instruction set is superset of 68HC11’s - upward compatible
programming model identical to 68HC11’s
8 MHz
ST9+
8/16-bit;
STMicroelectronics ^{register file}
evolution of the ST9
enhanced clock speed, instruction cycle time
enlarged memory space
25 MHz
ST9
8/16-bit;
STMicroelectronics ^{register file}
8/16-bit architecture; 8-bit register bus - 16-bit memory bus
register file programming model with 14 groups of sixteen 8-bit
registers, useable as 16-bit registers
modular paged registers for access to peripheral registers
12 MHz
H8/300
HITACHI
8/16-bit;
register file
RISC-like architecture and instruction set
register file programming model with sixteen 8-bit registers
10 MHz
68HC11
MOTOROLA
8-bit;
two
accumulators
market standard 8-bit MCU
accumulator programming model with two 8-bit accumulators or 4 MHz
one 16-bit accumulator, and two 16-bit index registers
68HC08
MOTOROLA
8-bit;
accumulator
superset of the 68HC05 - upward compatible
enhanced performance and instruction set
accumulator programming model with one 8-bit accumulator, and
one 16-bit index register
8 MHz
ST7
8-bit;
STMicroelectronics ^accumulator
upward compatible with the 68HC05
accumulator programming model with one 8-bit accumulator, and
two 8-bit index registers
4 MHz
8 MHz
80C51
INTEL, PHILIPS...
8-bit; register file
and accumulator
mixed accumulator and register file programming model with four
banks of eight 8-bit registers (include accumulator), and a 16-bit
data pointer
20 MHz
KS88
SAMSUNG
8-bit;
register file
core architecture superset of SUPER8’s; 8-bit register bus
register file programming model with 192 8-bit prime data registers, 8 MHz
and two register sets with system/peripheral/data registers
78K0
NEC
8-bit; register file
and accumulator
mixed accumulator and register file programming model with four
banks of eight 8-bit or four 16-bit registers (include accumulator)
10 MHz
1)
As the goal is to obtain the best of each MCU core, the maximum internal frequency (Freq) available, for each MCU, on
development board has been used (unless other specified). Note that results are directly proportional to this frequency.
A description of the MCU work environments is available in section 5.
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