AN910 Datasheet, PDF (28/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING

ST7 AND ST9 PERFORMANCE BENCHMARKING
7.3.1 80C51XA MCU core
Programming model
Register file
- banked registers
4 banks of four 16-bit registers
- global registers
four 16-bit registers (up to 12)
- others registers
16-bit program counter (up to 24-bit)
two 8-bit segment registers
16-bit system and user stack pointers
- special function registers
program status word, system configuration register
segment select register
data/extra/code segment registers
on-chip/off-chip peripheral and i/o port registers
- multitasking capabilities
context switching with banked registers
system and user modes
MOVE Rd,Rs
ADD Rd,#2
Instruction set
Cisc encoding
- CPI
2 cycles to 24 cycles
- average CPI
between 5 and 6 cycles
- IL
2 bytes to 6 bytes
- average IL
between 3 and 4 bytes
- special addressing modes
register access as bit, word, or doubleword
immediate with 11-bit addresses
indirect with 8/16-bit offset or auto-increment
- special instructions
exchange register contents
push/pull multiple registers
memory-to-memory moves
register indirect to reg. ind., both auto-increment
compare & branch like
decrement & branch like
80C51XA CPU
Cpu internal buses
16-bit mux. address/data/control bus
8/16-bit sfr bus (special function register)
Instruction processing
Prefetch mechanism
- 7-byte queue
- predecoding
- jump/branch address even alignment
addition of some 1-byte NOP instructions
- word operand even alignment
addition of some 1-byte NOP instructions
Arithmetic Logic Unit
+/x
16-bit datapath
- 8/16-bit operations
- special functions
8x8 unsigned multiplication
16x16 (un)signed multiplications
8/8 unsigned division
16/8 (un)signed divisions
32/16 (un)signed divisions
32-bit shifts
12 cycles
12 cycles
12 cycles
(12)14 cycles
(22)24 cycles
6 cycles
On-chip/Off-chip buses
- on-chip buses
16-bit address bus (up to 24-bit)
8/16-bit data memory bus
8/16-bit program memory bus
8/16-bit sfr bus
- off-chip buses
8/16-bit address bus (up to 24-bit)
8/16-bit multiplexed sfr/data/program mem. bus
the two buses may be multiplexed
the two buses are multiplexed with ports
Memory Spaces
Harvard organization
- segmented data/program memory spaces
data memory space
up to 255 segments of 64 kbytes each = 16 Mbytes
1-Kbyte zero page/segment (32 bytes bit addr.)
special function register space (logically separate)
512 bytes of on-chip registers (64 bytes bit addr.)
512 bytes of off-chip registers
program memory space
up to 255 segments of 64 kbytes each = 16 Mbytes
first 284-byte interrupt vector table = 71 interrupts
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