AN910 Datasheet, PDF (25/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING

ST7 AND ST9 PERFORMANCE BENCHMARKING
7 MCU CORE ARCHITECTURE ANALYSIS
This section presents, for the different MCUs, the main parameters of the core architecture
which are significant for benchmark result analysis.
7.1 PARAMETER DESCRIPTION
The significant parameters of core architecture are the following ones:
Programming model
Register file
Accumulator(s)
Mixed register file/accumulator
- list of registers (they may be outside the cpu)
- multitasking capabilities
MOVE Rd,Rs
ADD Rd,#2
LDAA #8, X
ADDA #A0
Instruction set
Cisc/Risc encoding
- Clock Per Instruction (CPI)
- average Clock Per Instruction
- Instruction Length (IL)
- average Instruction Length
- special addressing modes
- special instructions
CPU
Cpu internal buses
address bus size, data bus size
register bus (if any)
Instruction processing
Standard
Prefetch mechanism
- address alignment
- queue size
- predecoding (if any)
Arithmetic Logic Unit
+/x
datapath size
- standard operations
- special functions and performance
On-chip/Off-chip buses
- on-chip buses
address bus size
data/program memory bus sizes
register bus size (if any)
- off-chip buses (if any)
address bus size
data/program memory bus size
multiplexing
Memory Spaces
Harvard organization
Von Neumann organization
- special register space (if any)
- data/program memory spaces
- interrupt vector table location and size
25/51