AN910 Datasheet, PDF (11/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING

ST7 AND ST9 PERFORMANCE BENCHMARKING
4 RESULT ANALYSIS
This section is an analysis of computing performance and interrupt processing
performance results (for execution time and code size). Based on core architecture analysis
(see section 7), two comparisons are presented, pointing out the strong and weak points of
each MCU. The first concerns the high-end to medium-end MCUs versus ST9+. The
second concerns the medium-end to low-end MCUs versus ST7.
4.1 PRELIMINARY REMARK
Results show that the two different ratios, for execution time and code size, calculated with full
and reduced sets of tests, are in fact not very different. In most cases, the classification of the
MCUs is kept. Thus we can consider that the reduced set is sufficient to make the MCU
core comparison.
4.2 HIGH-END TO MEDIUM-END MCU ANALYSIS VERSUS ST9+
The Table 3 presents the strong and the weak points for high-end to medium-end MCUs,
compared to the ST9+ MCU.
Notes: ICT means Instruction Cycle Time and IL means Instruction Length.
Refer to paragraph <Italic>7.2.2 Average ICT/CPI and IL<Italic end> for details on
calculation.
Refer to paragraph <Italic>7.3.4 ST9+ MCU core<Italic end> to see the main characteristics of
the ST9+ MCU core.
4.2.1 Computing performance results
Regarding speed, the ST9+ MCU ranks at the top of 8/16-bit MCUs. This new version of the
ST9 has been improved on several points, including clock per instruction and clock speed.
These enhancements have considerably reduced its instruction cycle time. A large and
powerful register file organized in groups allow the ST9+ to perform strong computation
(with many registers), have an easy access to peripheral and i/o port registers (with paged
registers), and manage multitasking (with register group pointers). Addressing modes like
register pair, register indirect with pre/post-increment, and indexed give the ST9+ the ability to
perform 16-bit data computation and manipulation, easily manipulate tables and move
blocks. A new memory management unit enlarges the memory space up to 4 Mbytes. New
instructions have been added to handle this new space and improve the C-language
support.
11/51