AN910 Datasheet, PDF (30/51 Pages) STMicroelectronics – ST7 AND ST9 PERFORMANCE BENCHMARKING

ST7 AND ST9 PERFORMANCE BENCHMARKING
7.3.3 68HC12 MCU core
Programming model
Accumulators
- two 8-bit accumulators
useable as one 16-bit accumulator
- two 16-bit index registers
- others registers
16-bit program counter
16-bit stack pointer
condition code register
- multitasking capabilities
with memory expansion module
context switching with program page register
and program/data/extra windows
specific call and rtc instructions
LDAA #8, X
ADDA #A0
Instruction set
Cisc encoding
- CPI
1 cycle to 13 cycles
- average CPI
between 3 and 4 cycles
- IL
1 byte to 5 bytes
- average IL
between 3 and 4 bytes
- special addressing modes
auto pre/post-increment/decrement indexed
stack pointer and program counter indexed
indexed-indirect with 16-bit offset
accumulator offset indexed
- special instructions
exchange register contents
increment/decrement/test & branch like
memory-to-memory moves
extended ↔ extended
mac & min/max instructions
fuzzy logic support, table lookup and interpolate
68HC12 CPU
Cpu internal buses
16-bit address bus, 16-bit data bus
(to be confirmed)
Instruction processing
Prefetch mechanism
- 2-stage queue
2-word instruction queue
16-bit holding buffer if queue is full
- predecoding
- word operand even/odd alignment
no performance penalty if odd alignment
Arithmetic Logic Unit
+/x
20-bit datapath
- 8/16-bit operations
- special functions
8x8 unsigned multiplication
3 cycles
16x16 (un)signed multiplications 3 cycles
32/16 (un)signed divisions
(11)12 cycles
16/16 unsigned fractional division 12 cycles
16/16 (un)signed integer divisions 12 cycles
min/max of two 16-bit values
4 to 7 cycles
mac signed 16x16 to 32-bit mem. 13 cycles
8/16-bit table lookup and interpolate 10 cycles
(un)weighted product sum
8n cycles
On-chip/Off-chip buses
- on-chip buses
16-bit address bus
8/16-bit data/program memory bus
- off-chip buses
16-bit address bus
up to 22 bits with memory expansion module
8/16-bit data/program memory bus
the two buses are multiplexed with ports
Memory Spaces
Von Neumann organization
- linear data/program memory space
64 kbytes with first 256-byte zero page
peripheral registers in zero page
upper 128-byte interrupt vector table = 64 interrupts
- memory extension (Harvard organization)
program/data/extra mem. windows in linear space
up to 4-Mbyte memory space/window
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