TDA7333N Datasheet, PDF (32/36 Pages) STMicroelectronics – RDS/RBDS processor

Functional description
TDA7333N
Figure 19. Write rds_int registers in SPI mode, reading 1 register
CSN
CLK
DATAIN
{1,rds_int[6:0]}
DATAOUT
rds_int[7:0]
The content of the RDS registers is clocked out on DATAOUT pin in the following order:
rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0],
sinc4reg[7:0], testreg[7:0], pllreg4[7:0], pllreg3[7:0], pllreg2[7:0], pllreg1[7:0],
pllreg0[7:0].
For the meaning of each bit please refer to Section 3.8.
Note: 1 After 40 bit clocks the whole RDS data and flags are clocked out.
2 In SPI mode with applications having 2 or more SPI peripherals, it is necessary to inhibit the
clock line going to the TDA7333N when the CE line is kept high (not active).
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