TDA7333N Datasheet, PDF (27/36 Pages) STMicroelectronics – RDS/RBDS processor

TDA7333N
Functional description
3.9
I²C transfer mode
This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave
address select (SA).
The interface is capable of operating up to 400 kbits/s. If during the setup the system clock
fsys is smaller then 8.55 MHz, then the max. I²C speed decreases linear (e.i. if fsys = 4.275
MHz then the maximum I²C speed is 200 kbits/s for setup).
Data transfers follow the format shown in Figure 10. After the START condition (S), a slave
address is sent. The address is 7 bits long followed by an eighth bit which is a data direction
bit (R/_W).
A zero indicates a transmission (WRITE), a one indicates a request for data (READ).
The slave address of the chip is set to 001000S, where S is the least significant bit of the
slave address set externally via the pin SA_DATAOUT. This allows to choose between two
addresses in case of conflict with another device of the radio set.
Each byte has to be followed by an acknowledge bit (SDA low).
Data is transferred with the most significant (MSB) bit first.
A data transfer is always terminated by a stop condition (P) generated by the master.
Figure 10. I²C data transfer
SDA
SCL
S
START
CONDITION
1-7 8 9
ADDRESS R/W ACK
1-7 8 9
DATA
ACK
1-7 8
DATA
9
P
ACK/ACK STOP
CONDITION
3.9.1
Write transfer
Figure 11. I²C write transfer
S Slave address W A rds_int A rds_bd_ctrl A sinc4reg A testreg A P
from master to slave
from slave to master
S = start condition
W = write mode
Slave address = 001000S ( where S is the level of the pin
A = acknowledge bit
P = stop condition
SA_DATAOUT)
9 registers are available with write access (please refer to Section 3.8 for the meaning of
each bit).
To write registers, the external master must initiate the write transfer as described above,
then send the data to be written, and terminate the transfer by generating a stop condition.
27/36