TDA7333N Datasheet, PDF (20/36 Pages) STMicroelectronics – RDS/RBDS processor

Functional description
TDA7333N
Figure 9 describes the different states of the buffer with corresponding flags values:
1. This is the reset state, read (Rp) and write pointer (Wp) pointing at the same location 0.
The buffer is empty.
2. After the first buffer write operation, Wp points to the last written data (0, it is not
incremented) and the flag “bne” (buffer not empty) is set.
3. After next buffer write operation, Wp points to the last written data (3, incremented
address).
4. After buffer read operation, Rp points to incremented address (data to be read on the
next read cycle), following the Wp. As soon as Rp reaches the Wp (of value 3), it is not
incremented to 4 and flag “bne” is reset. Rp never goes ahead the Wp.
5. If the buffer is full (i.e. 24 blocks have been written before any read), flag “bfull” is set. If
no read operation is performed, on next write operation “bovf” (buffer overflow) is set,
and each subsequent write operation will overwrite the oldest data of the RAM buffer.
Rp is moved in front of the Wp.
6. If the whole content of the buffer has already been read, subsequent read operation will
always read the last written location - Rp never goes ahead the Wp.
3.8
Programming through serial bus interface
The serial bus interface is used to access the different registers of the chip. It is able to
handle both I²C and
SPI transfer protocols, the selection between the two modes is done thanks to the pin CSN:
– if the pin CSN is high, the interface operates as an I²C bus.
– if the pin CSN is asserted low, the interface operates as a SPI bus.
In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.
Depending on the transfer mode, external pins have alternate functions as following:
Table 6. External pins alternate functions
Pin
Function in SPI mode (CSN=0)
Function in I²C mode (CSN=1)
SCL_CLK
SDA_DATAIN
SA_DATAOUT
CLK (serial clock)
DATAIN (data input)
DATAOUT (data output)
SCL (serial clock)
SDA (data line)
SA (slave address)
13 registers are available with read or read/write access:
Table 7. Registers description
Register
Access
rights
Function
rds_int[7:0]
read/write interrupt source setting, synch., bne information
rds_qu[7:0]
read
quality counter, actual block name
rds_corrp[7:0]
rds_bd_h[7:0]
read
read
error correction status, buffer ovf information
high byte of current RDS block
rds_bd_l[7:0]
read
low byte of current RDS block
20/36