TDA7333N Datasheet, PDF (21/36 Pages) STMicroelectronics – RDS/RBDS processor

TDA7333N
Functional description
3.8.1
Table 7. Registers description (continued)
Register
Access
rights
Function
rds_bd_ctrl[7:0]
sinc4reg[7:0]
testreg[7:0]
pllreg4[7:0]
pllreg3[7:0]
pllreg2[7:0]
pllreg1[7:0]
pllreg0[7:0]
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
frequency, quality sensitivity, demodulator pll settings
sinc4 filter settings (for internal use only)
test modes (for internal use only)
PLL control register 4
PLL control register 3
PLL control register 2
PLL control register 1
PLL control register 0
The meaning of each bit is described below:
rds_int register
rds_int
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00 000 00 0
write bne ar_res synch itsrc2 itsrc1 itsrc0 int
r/w r r/w r r/w r/w r/w r
(1)
interrupt source
itsrc2
no interrupt
0
buffer not empty
0
buffer full
0
block A
0
block B
1
block D
1
TA
1
TA EON
1
itsrc1
itsrc0
0
0
01
10
11
00
01
10
11
Interrupt bit. It is set to one on every programmed interrupt. It is
reset by reading rds_int register. The inverted version is also
externally available on RDSINT pin.
itsrc[2:0] selects interrupt source (1).
Block A, B, D and TA, TA EON interrupts only if "synch" =1.
Synchronization information (refer to pages 13-15).
1: The module is already synchronized.
0: The module is synchronizing.
It is used to force a resynchronization. If it is set to one, the RDS
modules are forced to resynchronization state and the RAM buffer
address is reset.
This bit is reset automatically. It is read always as zero.
Buffer not empty.
1: At least one block is present in the RAM buffer.
0: The RAM buffer is empty.
rds_int, rds_bd_ctrl and pllreg4-0 write order.
This bit is only used in SPI mode and is read always as zero.
1: Update of rds_int, rds_bd_ctrl and pllreg4-0 with data shifted in.
0: No update of rds_int, rds_bd_ctrl and pllreg4-0.
(1) If the interrupt source is changed form block A, B,
D, TA, TA EON to another one "no interrupt" must be
set before to clear the previous interrupt acknowledge.
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