TDA7333N Datasheet, PDF (15/36 Pages) STMicroelectronics – RDS/RBDS processor

TDA7333N
Functional description
type of error can be measured with the five “cp” bits in order to classify the reliability of the
correction. Each bit set within “cp” means that one bit was corrected.
The two RDS data bytes rds_bd_h[7:0] and rds_bd_l[7:0] are available at the I²C/SPI
interface together with status bits rds_corrp[7:0] and rds_qu[7:0] giving reliability information
of the data (refer to Figure 5). rds_int[7:0] bits are used for interrupt and group and block
synchronization control. A software reset “ar_res” rds_int[5] can be used to force
resynchronization.
An endless 2 bit block counter (A, B, C or C’, D, A, B...) increments one step if a new RDS
block was received. During synchronization the block counter is set to the first identified
valid RDS block. Then every next RDS block must be of that type which is indicated by the
block counter “blk” rds_qu[3:2]. If this is not true, then the syndrome becomes not zero
(indicated by “synz” bit rds_qu[0]) and the “data_ok” bit rds_corrp[1] is not set. In case of
USA BRDS, four consecutive E blocks can be received which are indicated by the “e” bit
rds_qu[1].
The quality bit counter rds_qu[7:4] counts the bad quality marked RDS bits within a RDS
block.
The group and block synchronization module extracts also TA, TAEON information and
detects blocks types A, B, D (refer to page 21) which can be used as interrupt sources.
The TA interrupt is performed in two cases: If within block B the group 0A or 0B is indicated
and the TA bit is set or if within block B group 15B is indicated and the TA bit is set. The
TAEON interrupt is performed, if within block B group 14B is indicated and the TA bit is set.
The interrupts can be recognized on the interrupt flag “int” rds_int[0] (refer to Section 3.8.1).
The external open drain pin INTN (15) is the inverted version of the “int” flag.
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