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TDA7333N Datasheet, PDF (19/36 Pages) STMicroelectronics – RDS/RBDS processor
TDA7333N
Functional description
Figure 9. RAM buffer states
Rp Wp
1
32
Rp Wp
Rp Wp
Rp
4
23
22
0
1
2
write
23
22
0
1
2
write
23
22
0
1
2
23
22
0
1
2
21
21
21
Wp 21
Rp
bne = 0
bne = 0 1
bne = 1
3
bne = 1 0
3
bfull = 0
bfull = 0
bfull = 0
bfull = 0
Wp
bovf = 0
bovf = 0
bovf = 0
bovf = 0
read
reset status
5
Rp
Wp
23
22
0
1
2
21
bne = 1
3
bfull = 0 1
bovf = 0
write the first data
into buffer (internally)
Wp
write next three data into
buffer (internally)
Wp
Rp
read three data from buffer
(externally)
Rp
Wp
write
23
22
0
1
21
2
bne = 1
3
bfull = 1
bovf = 0 1
write
23 0
22
21
bne = 1
bfull = 1
bovf = 1
1
2
3
Wp
Rp
the write pointer reaches position
before the read pointer
(24 data written before any read)
the Wp reaches Rp
overflow flag is set
and the first data is
overwritten
Wp and Rp are
moving together
overwriting next data
read
6 Rp Wp
Rp
23
22
0
1
2
21
bne = 1 0
3
bfull = 0
bovf = 0
read
Rp Wp
23 0
22
21
bne = 0
bfull = 0
bovf = 0
1
2
3
the read pointer reaches but
doesn't go ahead the write pointer
the read pointer doesn't go
ahead the write pointer
Note : The read pointer Rp is driven externally through micro read access,
and the write pointer Wp is driven internally on every incoming block.
The different states of the buffer are indicated with the help of following flags:
– “bne”, buffer not empty. It is set as soon as one RDS block is written in the buffer,
and reset when reading rds_int register. This flag is a bit of rds_int register, it is
also an interrupt source (refer to Section 3.8.1).
– “bfull”, buffer full. It is set when 24 RDS blocks have been written, that is to say that
there is about 20 ms to read out the buffer content before an overflow occurs. This
flag is an interrupt source.
– “bovf”, buffer overflow. It is set if more than 24 RDS blocks are written. This flag is
a bit of register rds_corrp (refer to Section 3.8.3) and is cleared only by reading
the whole buffer (24 blocks).
An address reset of the RAM buffer can be performed by writing a 1 to “ar_res” bit in rds_int
register, it also forces a resynchronization.
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