SERCON410B Datasheet, PDF (27/34 Pages) STMicroelectronics – SERCOS INTERFACE CONTROLLER

SERCON410B
4.2 DATA STRUCTURES WITHIN THE RAM
In this RAM the first eleven words have a fixed meaning.
A10-1
0-1
2-9
10
Contents
COMPT0-1: Start of transmission blocks 0-1
SCPT0-7: Address service containers 0-7
NMSTERR: Error counter MST
The rest of the RAM can be divided into data structures as required.
4.2.1 Telegram Headers
A telegram header for receive telegram contains thefollowing five control words:
INDEX
0
1
2
Bit
0-7
8
9
10
11
12
13
14
15
0-15
0-15
Name
ADR
DMA
DBUF
VAL
ACHK
TCHK
RERR
0
0
TRT
TLEN
Function
Telegram address
Data storage in the internal RAM (DMA = 0) or DMA transfer
(DMA = 1)
Data in the RAM: single buffer (DBUF = 0) or double buffer (DBUF
= 1)
For single buffering (DMA = 0, DBUF = 0) or DMA transfer (DMA = 1):
telegram data is invalid (VAL = 0) or valid (VAL = 1); for double
buffering (DMA = 0, DBUF = 1): data in buffer 0 (VAL = 0) or buffer
1 (VAL = 1) is valid. Modified by controller at beginning and end of
receive telegrams.
Telegrams are received if the address is valid (ACHK = 1) or
independent on the received address (ACHK = 0). The received
address is stored at ADR.
The time of receiving is checked (TCHK = 1) or not checked
(TCHK = 0).
The last telegram was free of error (RERR = 0) or errored or not
received (RERR = 1).
Marker bit for telegram header of receive telegram.
Marker bit for telegram header.
Time for the start of telegram in µs after end of MST.
Length of telegram in data words (not including address).
0-9
PT
3
10-15
Word address within the RAM of the next telegram header or the
end marker.
(Not used)
4
0-15
NERR
Error counter
23/30
®