SERCON410B Datasheet, PDF (23/34 Pages) STMicroelectronics – SERCOS INTERFACE CONTROLLER

SERCON410B
CONTROL REGISTER ADDRESSES (Continued)
A6-1
3H
4H
5H
Bit
Name
12
DMAREQT
13
DMAREQR
14
IDLE
15
RECACTN
INT_n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0-7
8
9-12
13
14
15
CLR_INT_n
INT_RDIST
INT_FIBBR
INT_COMBLK0
INT_COMBLK1
INT_COMEND
INT_PHAS0
INT_PHASERR
INT_MSTEARLY
INT_MSTLATE
INT_MSTMISS
INT_TSTART
INT_TEND
INT_RWAIT
INT_RSTART
INT_REND
INT_RERR
INT_SC_0-7
INT_RMISS
INT_TIME0-3
INT_DIVCLK
INT_PROGERR
INT_NEWADR
R/W
Value
Function
R
0
DMA request of transmit FIFO inactive
1
DMA request of transmit FIFO active
R
0
DMA request of receive FIFO inactive
1
DMA request of receive FIFO active
R
Level at IDLE pin
R
Level at RECACTN pin
R
0
Interrupt event has not occurred
1
Interrupt flag active, interrupt event has occurred
W
0
Do not modify interrupt flag
1
Clear interrupt flag
R/W
Interrupt receive data distorted
R/W
Interrupt no receive data
R/W
Interrupt start transmission block 0
R/W
Interrupt start transmission block 1
R/W
Interrupt end of transmission block
R/W
Interrupt phase MST = 0.
R/W
Interrupt phase MST errored
R/W
Interrupt communication cycle start too early
R/W
Interrupt communication cycle start too late
R/W
Interrupt MST missing twice
R/W
Interrupt start of transmit telegram
R/W
Interrupt end of transmit telegram
R/W
Interrupt start waiting for receive telegram
R/W
Interrupt start of receive telegram
R/W
Interrupt end of receive telegram
R/W
Interrupt error of receive telegram
R/W
Interrupt service container
R/W
Interrupt receive telegram missing twice
R/W
Interrupt time TINT0-3
R/W
Interrupt DIVCLK signal
R/W
Interrupt programming error
R/W
Interrupt address change
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