SERCON410B Datasheet, PDF (24/34 Pages) STMicroelectronics – SERCOS INTERFACE CONTROLLER

SERCON410B
CONTROL REGISTER ADDRESSES (Continued)
A6-1
6H
Bit
Name
0-15 EN0_INT_n
7H
0-15 EN0_INT_n
8H
0-15 EN1_INT_n
9H
0-15 EN1_INT_n
OAH
OBH
0-7
PHAS0
8-15
0-7
8-15
PHAS1
PHASREC
RECADR
0
MSTEN
1
MSTMASTER
2
COMBLK0
0CH
3
COMBLK1
4
CON_CLK
5
ENCONCLK
6
POLCONCLK
7
CYC_CLK
8
ENCYCCLK
R/W
Value
Function
0
Interrupt flag does not activate INT0
R/W
1
Interrupt flag activates INT0
Bit assignment same as for address 4H
0
Interrupt flag does not activate INT0
R/W
1
Interrupt flag activates INT0
Bit assignment same as for address 5H
0
Interrupt flag does not activate INT1
R/W
1
Interrupt flag activates INT1
Bit assignment same as for address 4H
0
Interrupt flag does not activate INT1
R/W
1
Interrupt flag activates INT1
Bit assignment same as for address 5H
R/W
Phase for MST transmit (master) or MST
receive (slave) (reset value = 0FFH)
R/W
Phase for MST receive (slave)
(reset value = 0FFH)
R
Phase information of received MST
R
Address of receive telegram
0
MST is not transmitted or received
R/W
1
MST is transmitted or received (SERCOS
interface mode)
0
Receive MST (SERCOS interface slave)
R/W
1
Transmit and receive MST (SERCOS
interface master)
0
When phase = PHAS0 transmission block 0
R/W
is processed
1
When phase = PHAS0 transmission block 1
is processed
0
When phase = PHAS1 transmission block 0
R/W
is processed
1
When phase = PHAS1 transmission block 1
is processed
R
Level at CON_CLK pin
0
CON_CLK pin doesn’t become active
R/W
1
CON_CLK pin becomes active from TINT0 to
TINT1
R/W
0
Signal at CON_CLK is 1-active
1
Signal at CON_CLK is 0-active
R
Level at CYC_CLK pin
0
CYC_CLK pin does not trigger timing control
R/W
1
CYC_CLK pin triggers timing control after
TCYCSTART
20/30
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