SERCON410B Datasheet, PDF (10/34 Pages) STMicroelectronics – SERCOS INTERFACE CONTROLLER

SERCON410B
2 PIN DESCRIPTION
Table 1. SERCON410B I/O Port Function Summary
Signal (s)
D15-0
A15-0
Pin (s)
77-80,
82-85,
87-90,
92-95
56-59,
61-64,
66-69,
71-74
ALEL, ALEH 54, 53
RDN
51
WRN
BHEN
MCSN0,
MCSN1
PCSN0,
PCS1
BUSYN
52
75
46,47
48,49
45
DMAREQR
38
DMAACKRN
40
DMAREQT
39
DMAREQTN
41
ADMUX
96
BUSMODE0,
BUSMODE1
BUSWIDTH
97,98
99
IO
Function
Data bus: for 8-bit-wide bus interfaces, data is written to and read via D7-0,
I/O
for 16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address
which is stored in the address latch with ALEL and ALEH is input via D15-0.
Address bus: when ADMUX is 0 the pins are inputs, when ADMUX is 1, they
are outputs for the address stored with ALEL (A7-0) and ALEH (A15-8). In
I/O
the 8-bit bus mode, A0 distinguishes which byte is transmitted via
D7-0 (depends on BYTEDIR). In the 16-bit bus mode, data is tansferred via
D7-0 only when A0 is 0. A10-1 selects the words of the internal RAM; A6-
1the control registers.
Address latch enable, low and high, active high: they are only used when
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ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to
the address bus, when ALEL/ALEH = 0, they store the address. When
ADMUX is 0, ALEL/ALEH have to be connected to V_DD.
Read: for the Intel bus interface, data is read when RDN is 0. For the
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Motorola bus interface, data is read or written to when RDN is 0
(BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1).
Write: for the Intel bus interface, data is written to when WRN is 0. For the
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Motorola bus interface, WRN selects read (WRN = 1) and write (WRN = 0)
operations of the data bus.
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Byte high enable, active low: in the 16-bit bus mode, data is transferred via
D15-8 when BHEN is 0.
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Memory chip select, active low: to access the internal RAM MCSN0 and
MCSN1 must be 0.
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Periphery chip select, active low (PCSN0) and active high (PCSN1): to
access the control registers PCSN0 must equal 0 and PCS1 must equal 1.
RAM busy, active low: becomes active if an access to an address of the
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dual port RAM is performed simultaneously to an access to the same
memory location by the internal telegram processing.
DMA request receive, active high: becomes active if data from the receive
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FIFO can be read. At the beginning of the read operation of the last word of
the receive FIFO, DMAREQR becomes inactive.
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DMA acknowledge receive, active low: when DMAACKRN is 0, the receive
FIFO is read, independent of the levels on A6-1 and the chip select signals.
DMA request transmit, active high: becomes active when data can be
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written to the transmit FIFO. DMAREQT becomes inactive again at the
beginning of the last write access to the transmit FIFO.
DMA acknowledge transmit, active low: when DMAACKTN is 0, the
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transmit FIFO is written to when there is a bus write access independent of
the levels on A6-1 and the chip select signals.
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Address data bus: when ADMUX is 0 A15-0 are the address inputs, when
ADMUX is 1 A15-0 are the outputs of the address latch.
Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read,
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WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data
strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe
(BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1).
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Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).
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