W305B Datasheet, PDF (7/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Bit
Description
Bit
29
30:37
38
39
Byte Read Protocol
Description
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
W305B Serial Configuration Map
The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (reserved and N/A) should be written
to a “0” level.
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
-
SEL4
-
SEL3
-
SEL2
0
See Table 5
0
See Table 5
0
See Table 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
SEL1
0
See Table 5
-
SEL0
0
See Table 5
-
Spread Select2
0
‘000’ = Normal (spread off)
-
Spread Select1
0
‘001’ = Test Mode
-
Spread Select0
0
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = ±0.5%
‘110’ = ±0.25%
‘111’ = ±0.38%
Byte 1: Control Register 1
Bit
Bit 7
Pin#
23
Bit 6
3
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
-
Bit 1
3
Bit 0
-
Name
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
REF2X
Reserved
Default
X
X
X
X
X
0
1
0
Description
Latched FS[4:0] inputs. These bits are read only.
Reserved
(Active/Inactive)
Reserved
Byte 2: Control Register 2
Bit
Bit 7
Bit 6
Pin#
20
19
Bit 5
18
Bit 4
16
Name
PCI7
PCI6
PCI5
PCI4
Default
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Rev 1.0, November 20, 2006
Page 7 of 20