W305B Datasheet, PDF (2/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF2X/FS3
3
I/O Reference Clock with 2x Drive/Frequency Select 3. 3.3V 14.318-MHz clock
output. This pin also serves as the select strap to determines device operating
frequency as described in Table 5.
X1
4
I Crystal Input. This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
5
O Crystal Output. An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
PCI0/FS0
11
I/O PCI Clock 0/Frequency Selection 0. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI1/FS1
12
I/O PCI Clock 1/Frequency Selection 1. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI2/FS2
13
I/O PCI Clock 2/Frequency Selection 2. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI3:7
15, 16, 18, 19, 20 O PCI Clock 3 through 7. 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individ-
ually turned off via SMBus interface.
3V66_0:2
7, 8, 9
O 66-MHz Clock Output. 3.3V output clocks. The operating frequency is
controlled by FS0:4 (see Table 5).
48MHz
22
O 48MHz. 3.3V 48-MHz non-spread spectrum output.
48MHz/FS4
23
I/O 48-MHz Output/Frequency Selection 4. 3.3V 48-MHz non-spread spectrum
output. This pin also serves as the select strap to determine device operating
frequency as described in Table 5.
24_48MHz/SEL24
24
_48MHz#
I/O 24- or 48-MHz Output/Select 24 or 48MHz. 3.3V 24 or 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the output
frequency for 24_48MHz output.
RST#
30
O Reset#. Open-drain RESET# output.
(open-d
rain)
CPU0:1
52, 51
O CPU Clock Outputs. Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:4. Voltage swing is set by
VDDQ2.
SDRAM0:12,
49, 48, 47, 44,
SDRAM Clock Outputs. 3.3V outputs for SDRAM and chipset. The operating
43, 42, 41, 38, O frequency is controlled by FS0:4 (see Table 5).
37, 36, 35, 32, 31
APIC
55
O Synchronous APIC Clock Outputs. Clock outputs running synchronous with
the PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
26
I/O Data pin for SMBus circuitry.
SCLK
29
I Clock pin for SMBus circuitry.
VDDQ3
2, 6, 17, 25, 28,
34, 40, 46
P 3.3V Power Connection. Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
53, 56
P 2.5V Power Connection. Power supply for APIC and CPU output buffers.
Connect to 2.5V.
GND
1, 10, 14, 21, 27, G Ground Connections. Connect all ground pins to the common system ground
33, 39, 45, 50, 54
plane.
Rev 1.0, November 20, 2006
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