W305B Datasheet, PDF (12/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
Byte 14: Programmable Frequency Select M-Value Register
Bit
Name
Default
Description
Bit 7
Pro_Freq_EN
0
Programmable output frequencies enabled
0 = disabled
1 = enabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
0
If Prog_Freq_EN is set, W305B will use the values programmed in
0
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is
0
updated.
0
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same
0
frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B
0
will use the frequency ratio stated in the SEL[4:0] register.
W305B supports programmable CPU frequency ranging from 50 MHz to
0
248 MHz.
Byte 15: Reserved Register
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
-
Reserved
-
Reserved
-
Reserved
0
Reserved
0
Reserved
0
Reserved
Bit 4
Bit 3
Bit 2
-
Reserved
-
Reserved
-
Reserved
0
Reserved
0
Reserved
0
Reserved
Bit 1
Bit 0
-
Reserved
-
Reserved
1
Reserved. Write with ‘1’
1
Reserved. Write with ‘1’
Byte 16: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin#
-
-
-
-
-
-
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 17: Reserved Register
Bit
Bit 7
Bit 6
Pin#
-
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Rev 1.0, November 20, 2006
Page 12 of 20