W305B Datasheet, PDF (17/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
AC Electrical Characteristics T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2= 2.5V±5%f_XTL = 14.31818 MHz^[2]
66.6-MHz Host 100-MHz Host 133-MHz Host
Parameter
Description
Min. Max. Min. Max. Min.
Max. Unit Notes
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
Host/CPUCLK Period
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
15.0 15.5 10.0 10.5
7.5
5.2
N/A
3.0
N/A
1.87
5.0
N/A
2.8
N/A
1.67
0.4
1.6
0.4
1.6
0.4
0.4
1.6
0.4
1.6
0.4
8.0
ns 4
N/A
ns 4,7
N/A
ns 5
1.6
ns
1.6
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
SDRAM CLK Period
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
10.0 10.5 10.0 10.5 10.0
3.0
N/A
3.0
N/A
3.0
2.8
N/A
2.8
N/A
2.8
0.4
1.6
0.4
1.6
0.4
0.4
1.6
0.4
1.6
0.4
10.5
N/A
N/A
1.6
1.6
ns 4
ns 4
ns 5
ns
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
APIC CLK Period
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
60.0 64.0 60.0 N/A
60.0
64.0
ns 4
25.5 N/A 25.5 N/A
25.5
N/A
ns 4
25.3 N/A 25.30 N/A 25.30
N/A
ns 5
0.4
1.6
0.4
1.6
0.4
1.6
ns
0.4
1.6
0.4
1.6
0.4
1.6
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
15.0 16.0 15.0 16.0 15.0
5.25 N/A 5.25 N/A
5.25
5.05 N/A 5.05 N/A
5.05
0.5
2.0
0.5
2.0
0.5
0.5
2.0
0.5
2.0
0.5
16.0
N/A
N/A
2.0
2.0
ns 4, 5
ns 4
ns 5
ns
ns
T_Period
T_HIGH
T_LOW
T_RISE
T_FALL
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
30.0 N/A 30.0 N/A
30.0
12.0 N/A 12.0 N/A
12.0
12.0 N/A 12.0 N/A
12.0
0.5
2.0
0.5
2.0
0.5
0.5
2.0
0.5
2.0
0.5
N/A
ns 4, 7
N/A
ns 4
N/A
ns 5
2.0
ns
2.0
ns
tp_ZL, tp_ZH Output Enable Delay (All outputs) 1.0
10.0
1.0
10.0
1.0
tp_LZ, tp_ZH Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
t_stable
All Clock Stabilization from
Power-Up
3
3
10.0
ns
10.0
ns
3
ms
Notes:
4. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when V_DDQ3 achieves its nominal operating level (typical condition V_DDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
6. T_RISE and T_FALL are measured as a transition through the threshold region V_ol = 0.4V and V_oh = 2.0V (1 mA) JEDEC specification.
7. T_LOW is measured at 0.4V for all outputs.
8. T_HIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
Rev 1.0, November 20, 2006
Page 17 of 20