W305B Datasheet, PDF (10/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
Bit 4
RST_EN_WD
0
This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 3
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
WD_TO_STATUS
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1
WD_EN
0
0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency
mode.
1 = Enable Watchdog timer. It will start counting down after a frequency change
occurs.
Note: W305B will generate system reset, re-load a recovery frequency, and
lock itself into a recovery frequency mode after a Watchdog timer time-out
occurs. Under recovery frequency mode, W305B will not respond to any attempt
to change output frequency via the SMBus control bytes. System software can
unlock W305B from its recovery frequency mode by clearing the WD_EN bit.
Bit 0
Reserved
0
Reserved
Byte 10: Skew Control Register
Bit
Name
Default
Description
Bit 7
Bit 6
Bit 5
CPU_Skew2
CPU_Skew1
CPU_Skew0
0
CPU skew control
0
000 = Normal
001 = –150 ps
0
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SDRAM_Skew2
SDRAM_Skew1
SDRAM_Skew0
AGP_Skew1
AGP_Skew0
0
SDRAM skew control
0
000 = Normal
001 = –150 ps
0
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
0
AGP skew control
0
00 = Normal
01 = –150ps
10 = +150ps
11 = +300ps
Rev 1.0, November 20, 2006
Page 10 of 20