W305B Datasheet, PDF (18/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic

W305B
Group Skew and Jitter Limits
Output Group
CPU
SDRAM
APIC
48MHz
3V66
PCI
REF
Pin-Pin Skew Max.
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
Cycle-Cycle Jitter
250 ps
250 ps
500 ps
500 ps
500 ps
500 ps
1000 ps
Duty Cycle
45/55
45/55
45/55
45/55
45/55
45/55
45/55
Nom Vdd
2.5V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
Skew, Jitter
Measure Point
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
Output
Buffer
Test Point
Clock Output Wave
2.0
1.25
2.5V Clocking
Interface
0.4
T_HIGH
Test Load
T_PERIOD
Duty Cycle
T_RISE
T_FALL
T_LOW
T_HIGH
T_PERIOD
Duty Cycle
2.4
3.3V Clocking ^1.5
Interface ^0.4
T_RISE
T_FALL
T_LOW
Figure 6. Output Buffer
Layout Example
Rev 1.0, November 20, 2006
Page 18 of 20