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W305B Datasheet, PDF (1/20 Pages) Cypress Semiconductor – Frequency Controller with System Recovery for Intel Integrated Core Logic
W305B
Frequency Controller with System Recovery for Intel£ Integrated
Core Logic
Features
• Single chip FTG solution for Intel Solano/810E/810
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for SDRAM and PCI
output clocks
• Programmable output skew between CPU, AGP, PCI
and SDRAM
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Two copies of CPU clock
• Thirteen copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Three copies of 66-MHz outputs
• Three copies of 48-MHz outputs
• One copy of double strength 14.31818-MHz reference
clock
• One RESET output for system recovery
• SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
Block Diagram
X1
X2
SDATA
SCLK
(FS0:4)
XTAL
OSC
PLL REF FREQ
SMBus
Logic
Divider,
Delay,
and
Phase
Control
Logic
PLL 1
PLL2
/2
VDDQ3
REF2X/FS3
VDDQ2
CPU0:1
2
APIC
VDDQ3
3V66_0:2
3
PCI0/FS0
PCI1/FS1
PCI2/FS2
PCI3:7
5
SDRAM0:12
13
RST#
VDDQ3
48MHz
48MHz/FS4
24_48MHz/SEL24_48MHz#
Pin Configuration[1]
GND 1
VDDQ3 2
REF2X/FS3^ 3
X1 4
X2 5
VDDQ3 6
3V66_0 7
3V66_1 8
3V66_2 9
GND 10
PCI0/FS0^ 11
PCI1/FS1^ 12
PCI2/FS2^ 13
GND 14
PCI3 15
PCI4 16
VDDQ3 17
PCI5 18
PCI6 19
PCI7 20
GND 21
48MHz 22
48MHz/FS4^ 23
24_48MHz/SEL24_48MHz#* 24
VDDQ3 25
SDATA 26
GND 27
VDDQ3 28
56 VDDQ2
55 APIC
54 GND
53 VDDQ2
52 CPU0
51 CPU1
50 GND
49 SDRAM0
48 SDRAM1
47 SDRAM2
46 VDDQ3
45 GND
44 SDRAM3
43 SDRAM4
42 SDRAM5
41 SDRAM6
40 VDDQ3
39 GND
38 SDRAM7
37 SDRAM8
36 SDRAM9
35 SDRAM10
34 VDDQ3
33 GND
32 SDRAM11
31 SDRAM12
30 RST#
29 SCLK
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH or LOW.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 20
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