LAN9215_12 Datasheet, PDF (84/144 Pages) SMSC Corporation – 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

5.3.9
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section
3.12.8, "Stopping and Starting the Transmitter," on page 58 and Section 3.13.4, "Stopping and
Starting the Receiver," on page 62 for details on stopping the transmitter and receiver.
BITS
DESCRIPTION
31-25 Reserved
24 AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
23-21 Reserved
20
16-19
15-7
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 86 for more information.
Reserved
6-5 PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
[6] [5]
MII Clock Source
---------------------------------------------------
00
Internal PHY
01
External MII Port
10
Clocks Disabled
11
Internal PHY
Notes:
„ This field does not control multiplexing of the SMI port or other MII signals.
„ There are restrictions on the use of this field. Please refer to Section 3.11,
"MII Interface - External MII Switching," on page 46 for details.
4 Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note: This bit does not control the multiplexing of other MII signals.
TYPE
RO
RO
RO
R/W
R/W
RO
R/W
R/W
DEFAULT
-
AMDIX
Strap
Pin
-
0
5h
-
00b
0
Revision 2.9 (03-01-12)
84
DATASHEET
SMSC LAN9215