LAN9215_12 Datasheet, PDF (31/144 Pages) SMSC Corporation – 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
Table 3.2 Wake-Up Frame Filter Register Structure
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
Reserved
Filter 3
Command
Reserved
Filter 2
Command
Reserved
Filter 1
Command
Reserved
Filter 0
Command
Filter 3 Offset
Filter 2 Offset
Filter 1Offset
Filter 0 Offset
Filter 1 CRC-16
Filter 0 CRC-16
Filter 3 CRC-16
Filter 2 CRC-16
The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether
or not this is a wake-up frame. Table 3.3, describes the byte mask’s bit fields.
FIELD
31
30:0
Table 3.3 Filter i Byte Mask Bit Definitions
FILTER I BYTE MASK DESCRIPTION
DESCRIPTION
Must be zero (0)
Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset
+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.
The Filter i command register controls Filter i operation. Table 3.4 shows the Filter I command register.
FIELD
3
2:1
0
Table 3.4 Filter i Command Bit Definitions
FILTER i COMMANDS
DESCRIPTION
Address Type: Defines the destination address type of the pattern. When bit is set, the pattern
applies
only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.
RESERVED
Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.
The Filter i Offset register defines the offset in the frame’s destination address field from which the
frames are examined by Filter i. Table 3.5 describes the Filter i Offset bit fields.
SMSC LAN9215
31
DATASHEET
Revision 2.9 (03-01-12)