LAN9215_12 Datasheet, PDF (33/144 Pages) SMSC Corporation – 16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support

16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
3.6
3.6.1
3.6.2
3.6.3
3.6.4
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9215 is in the D0 or D1
power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the
D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when
the device enters the D1 state.
Host Bus Operations
Bus Writes
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit write). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next write is performed to the other word. If a write to the
same word is performed, the LAN9215 disregards the transfer.
Bus Reads
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD
transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot
change during a sixteen bit read). No ordering requirements exist. The processor can access either
the low or high word first, as long as the next read is performed from the other word. If a read to the
same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The
LAN9215 will reset its read counters and restart a new cycle on the next read.
Big and Little Endian Support
The LAN9215 supports “Big-” or “Little-Endian” processors with either 16 or 32-bit busses. To support
big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes.
Word Swap Function
Internally the LAN9215 is 32-bits wide. The LAN9215 supports a Word Swap Function. This feature is
controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD_SWAP—Word
Swap Control," on page 93. This register affects how words on the data bus are written to or read from
the Control and Status Registers and the Transmit and Receive Data/Status FIFOs. Refer to Table 3.7,
"Word Swap Control(16-bit mode only)" below for more details. Whenever the LAN9215 transmits data
from the Transmit Data FIFO to the network, the low order word is always transmitted first, and when
the LAN9215 receives data from the network to the Receive Data FIFO, the low-order word is always
received first.
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SMSC LAN9215
33
DATASHEET
Revision 2.9 (03-01-12)