COM20019 Datasheet, PDF (77/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

outside the CPU. It's not synchronized between
the CPU and COM20019. Thus, changing the
CKP3-1 timing does not synchronize with the
internal clocks of Pre-Scalar, and changing
CKP3-1 may cause spike noise to appear on the
output clock line.
Setting the EF bit will include flip-flops inserted
between the Configuration register and Pre-
Scalar for synchronizing the CKP3-1 with Pre-
Scalar’s internal clocks.
C) Shorten The Write Interval Time To The
Command Register
The COM20019 limits the write interval time for
continuous writing to the Command register. The
minimum interval time is changed by the Data
Rate. It's 800 nS at the 312.5 Kbps and 1.6 μS at
the 156.25 Kbps. This 1.6 μS is very long for
CPU.
Setting the EF bit will change the clock source
from OSCK clock (8 times frequency of data
rate) to XTAL clock which is not changed by the
data rate, such that the minimum interval time
becomes 100 nS.
D) Eliminate The Write Prohibition Period For
The Enable Tx/Rx Commands
The COM20019 has a write prohibition period for
writing the Enable Transmit/Receive Commands.
This period is started by the TA or RI bit (Status
Reg.) returning to High. This prohibition period is
caused by setting the TA/RI bit with a pulse
signal. It is 3.2 μS at 156.25 Kbps. This period
may be a problem when using interrupt
processing. The interrupt occurrs when the RI bit
returns to High. The CPU writes the next Enable
Receive Command to the other page
immediately. In this case, the interval time
between the interrupt and writing Command is
shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to
return to High upon release of the pulse signal
for setting the TA/RI bit, instead of at the start of
the pulse. This is illustrated in figure 23 on the
following page.
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