COM20019 Datasheet, PDF (17/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

Diagnostic register and generates the starting
pulse of the RAM Arbitration. Typical delay time
between nRD and nRD1 is around 15nS and
between nRD1 and nRD2 is around 10nS.
RBUSTMG=1, Enabled.
In the MOTOROLA CPU mode (DIR, nDS
mode), the same modifications apply.
Longer pulse widths are needed due to these
delays on nRD signal. However, the CPU can
insert some wait cycles to extend the width
without any impact on performance.
The RBUSTMG bit was added to Disable/Enable
the High Speed CPU Read function. It is defined
as: RBUSTMG=0, Disabled (Default);
RBUSTMG BIT
BUS TIMING MODE
0
Normal Speed CPU Read and Write
1
High Speed CPU Read and Normal Speed CPU Write
TRANSMISSION MEDIA INTERFACE
The bottom halves of Figures 2 and 3 illustrate the
COM20019 interface to the transmission media
used to connect the node to the network. Table 1
lists different types of cable which are suitable for
ARCNET applications.¹
The user may interface to the cable of choice in
one of three ways:
1 _{Please refer to TN7-5 – Cabling Guidelines for}
the COM20020 ULANC, available from SMSC, for
recommended cabling distance, termination, and
node count for ARCNET nodes.
17
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