COM20019 Datasheet, PDF (32/81 Pages) SMSC Corporation – Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM

DATA
000r p110
0000 1000
COMMAND
Clear Flags
Clear
Receive
Interrupt
DESCRIPTION
This command resets certain status bits of the COM20019. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON status
bit.
This command is used only in the Command Chaining operation.
Please refer to the Command Chaining section for definition of
this command.
BIT
BIT NAME
7 Read Data
6 Auto Increment
5-3 (Reserved)
2-0 Address 10-8
Table 7 - Address Pointer High Register
SYMBOL
DESCRIPTION
RDDATA
This bit tells the COM20019 whether the following access
will be a read or write. A logic "1" prepares the device for a
read, a logic "0" prepares it for a write.
AUTOINC
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic
increment of the pointer after each access, while a logic "0"
disables this function. Please refer to the Sequential
Access Memory section for further detail.
These bits are undefined.
A10-A8
These bits hold the upper three address bits which provide
addresses to RAM.
BIT
BIT NAME
7-0 Address 7-0
Table 8 - Address Pointer Low Register
SYMBOL
DESCRIPTION
A7-A0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
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